1. Field of the Invention
The invention relates to a digital electronic design system, particularly to a hybrid electronic design system and a reconfigurable connection matrix thereof.
2. Description of the Prior Art
In the digital electronic design field, the IC designer can employ Verilog or VHDL to compile the Register Transfer Level (RTL) for hardware simulation. However, after entering into the Systematic-on-a-Chip (SoC) era, there are millions even hundred millions of Gate Count inside the SoC. The IC designer is difficult to finish the design from RTL abstraction level quickly under this situation.
Upon designing the SoC in RTL abstraction level, it is often necessary to consume a lot of time and calculation resources to carry out the simulation and verification, so that the time-to-market will be influenced. In addition, the IC designer will often face the predicaments, such as the transformation of different design tools, and difficult integration among the programming languages. Thus, the RTL verification is still a bottleneck in the digital circuit design.
Although some solutions are able to be adopted to support the functional model of fast and complete SoC simulation at present, it is often necessary to use SystemC and TLM 2.0 to develop the ESL virtual model of existing IP again, which will consume a lot of time and manpower. In addition, the execution speed is still slower than the physical IP.